Thermally enhanced thin semiconductor package

ABSTRACT

A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.

CROSS-REFERENCES TO RELATED APPLICATIONS

Not Applicable

BACKGROUND

Semiconductor die packages are known in the semiconductor industry, butcould be improved. For example, electronic devices such as wirelessphones and the like are becoming smaller and smaller. It is desirable tomake thinner semiconductor die packages so that they can be incorporatedinto such electronic devices. It would also be desirable to improve uponthe heat dissipation properties of conventional semiconductor diepackages.

Another technical challenge that exists is in the formation of suchsemiconductor die packages. A clip and a leadframe may sandwich asemiconductor die in an exemplary semiconductor die package. If the clipand the leadframe are not properly aligned with each other and thesemiconductor die, then the manufactured semiconductor die package couldbe defective and rework may be needed.

Embodiments of the invention address these and other problems,individually and collectively.

BRIEF SUMMARY

Embodiments of the invention are directed to semiconductor die packages,methods for making semiconductor die packages, and assemblies andsystems using such semiconductor die packages.

One embodiment of the invention is directed to a semiconductor diepackage. The semiconductor die package includes a semiconductor diecomprising an input at a first top semiconductor die surface and anoutput at a second bottom semiconductor die surface. A leadframe havinga first leadframe surface and a second leadframe surface opposite thefirst leadframe surface is in the semiconductor die package and iscoupled to the first top semiconductor die surface. A clip having afirst clip surface and a second clip surface is coupled to the secondbottom semiconductor die surface. A molding material having exteriormolding material surfaces covers at least a portion of the leadframe,the clip, and the semiconductor die. The first leadframe surface and thefirst clip surface are exposed by the molding material, and the firstleadframe surface, the first clip surface, and the exterior moldingmaterial surfaces of the molding material form exterior surfaces of thesemiconductor die package.

Another embodiment of the invention is directed to a method for forminga semiconductor die package. The method comprises obtaining asemiconductor die comprising an input at a first top semiconductor diesurface and an output at a second bottom semiconductor die surface, andattaching a leadframe having a first leadframe surface and a secondleadframe surface opposite the first leadframe surface to thesemiconductor die. The second leadframe surface is coupled to the firsttop semiconductor die surface. A clip is attached to the second bottomsemiconductor die surface. The clip has a first clip surface and asecond clip surface. A molding material is molded around at least aportion of the leadframe, the clip, and the semiconductor die. Aftermolding, the first leadframe surface and the first clip surface areexposed by the molding material. The first leadframe surface, the firstclip surface, and the exterior molding material surfaces of the moldingmaterial form exterior surfaces of the semiconductor die package.

These and other embodiments of the invention are described in furtherdetail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a top perspective view of a semiconductor die packageaccording to an embodiment of the invention.

FIG. 2 shows a bottom perspective view of the semiconductor die packageshown in FIG. 1.

FIG. 3 shows a top perspective view of a semiconductor die packageaccording to an embodiment of the invention with the outline of themolding material shown.

FIG. 4 shows a bottom perspective view of a semiconductor die packageaccording to an embodiment of the invention with the outline of themolding material shown.

FIG. 5 shows a top perspective view of a semiconductor die packageaccording to an embodiment of the invention with a portion of themolding material being removed.

FIG. 6 shows a bottom perspective view of a semiconductor die packageaccording to an embodiment of the invention with a portion of themolding material being removed.

FIG. 7 shows a side cross-sectional view of a semiconductor die packageaccording to an embodiment of the invention.

FIG. 8 shows a front cross-sectional view of a semiconductor die packageaccording to an embodiment of the invention.

FIG. 9 shows an exploded view of a semiconductor die package accordingto an embodiment of the invention.

FIG. 10 shows a top view of a semiconductor die package according to anembodiment of the invention.

FIG. 11 shows a top perspective view of a leadframe structure attachedto a frame.

FIG. 12 shows a bottom perspective view of a thermal drain clip.

FIG. 13 shows a bottom perspective view of an internal frame die attachpad area.

FIG. 14 shows a bottom perspective view of an assembled frame with anattached thermal drain clip.

FIG. 15 is a top perspective view of an assembled frame with an attachedthermal drain clip.

FIG. 16 is a top perspective view of an assembled frame with an attachedthermal drain clip, after molding.

FIG. 17 is a bottom perspective view of an assembled frame with anattached thermal drain clip, after molding.

FIG. 18 is a side, cross-sectional view of an embodiment of theinvention after assembly and molding.

FIGS. 19( a) and 19(c) show die bonding and layouts.

FIGS. 20( a)-20(k) show portions of a semiconductor die package as it isbeing formed.

FIG. 21 shows a semiconductor die comprising a vertical MOSFET with atrenched gate.

In the Figures, like numerals designate like elements, and thedescriptions of like elements may not be repeated in some instances.

DETAILED DESCRIPTION

One embodiment of the invention is directed to a semiconductor diepackage. The semiconductor die package includes a semiconductor diecomprising an input (e.g., a source region) at a first top semiconductordie surface and an output (e.g., a drain region) at a second bottomsemiconductor die surface. A leadframe having a first leadframe surfaceand a second leadframe surface opposite the first leadframe surface isin the semiconductor die package and is coupled to the first topsemiconductor die surface. A clip (e.g., a drain clip) having a firstclip surface and a second clip surface is coupled to the second bottomsemiconductor die surface. A molding material having exterior moldingmaterial surfaces covers at least a portion of the leadframe, the clip,and the semiconductor die. The first leadframe surface and the firstclip surface are exposed by the molding material, and the firstleadframe surface, the first clip surface, and the exterior moldingmaterial surfaces of the molding material may form exterior surfaces ofthe semiconductor die package.

FIG. 1 shows a top perspective view of a semiconductor die package 10according to an embodiment of the invention. The semiconductor diepackage 10 comprises a leadframe 214 comprising a source lead structure214(a) and a gate lead structure 214(b). The source lead structure214(a) comprises a source pad 14, an exposed source surface 14(a) (whichmay be an example of at least part of a first leadframe surface), andsource leads 12. The leadframe 214 may also comprise a gate leadstructure comprising a gate lead 11. An exposed thermal clip 15 is alsoshown, and will be described in further detail below with respect toFIG. 2. A molding material 13 may be formed on at least a portion of theleadframe 214, the clip 215, and a semiconductor die (not shown) thatlies between the leadframe 214 and the clip 15. The molding material 13may be formed using any suitable material including an epoxy basedmolding material. If desired, a heatsink (not shown) could be placed ontop of the surface 14(a) to improve heat dissipation properties.

As shown in FIG. 1, a top exterior surface of the molding material 13 ofthe semiconductor die package 10 is substantially coplanar with andexposes the exposed source pad surface 14(a). Extensions to the sourceleads 12 (as well as the gate lead 11) are also exposed by the moldingmaterial 13 in this example. Thus, the topmost surface of the packagemay be formed at least in part by the exposed source surface 14(a) andthe top exterior surface of the molding material 13. This particularconfiguration results in a very thin semiconductor die package, withgood heat dissipation properties. Heat can dissipate through the gatelead 11, the source lead 12, and the exposed thermal clip 15.

FIG. 2 shows a bottom view of the semiconductor die package 10 shown inFIG. 1. As shown, a bottom clip surface 15(a) (which may be an exampleof a first clip surface) of the thermal clip 15 may be exposed by themolding material 13. The bottom clip surface 15(a) may be substantiallycoplanar with the bottom surface of the molding material 13. The ends ofthe leads 11, 12 may also be substantially coplanar with the bottom clipsurface 15(a) so that the semiconductor die package 10 can be mounted toa printed circuit board or the like.

In the embodiment shown in FIG. 2, the leads 11, 12 may extend out ofthe molding material 13 from one end of the semiconductor die package10, while a portion of the clip 15 may extend out of the moldingmaterial 13 from the opposite end of the semiconductor die package 10.Thus, the package 10 shown in FIG. 2 is a leaded package. In otherembodiments of the invention, however, “leadless” packages could beproduced. A leadless package may still include leads, but they may notextend past the lateral surfaces of the molding material 13 at all or toany appreciable degree.

FIG. 3 is a top perspective view of the semiconductor die package shownin FIG. 1 with the outline of the molding material being shown by dottedlines. FIG. 4 shows a bottom perspective view of the semiconductor diepackage shown in FIG. 1 with the outline of the molding material beingshown by dotted lines. FIGS. 3 and 4 more clearly show a leadframecomprising a gate lead structure 11 and a source lead structure 12. Thegate lead structure 11 and the source lead structure 12 are electricallyisolated from each other.

A semiconductor (e.g., silicon) die 32 is sandwiched between theleadframe and a thermal drain clip 15. The thermal clip 15 and theleadframe may be electrically coupled to an output region in thesemiconductor die 32 in the semiconductor die package 10.

The leadframe 214 and the thermal drain clip 15 may be formed of anysuitable electrically conductive material including copper, aluminum,noble metals and alloys thereof. The leadframe and the thermal drainclip 15 may also be plated with solderable layers (e.g., underbumpmetallurgy layers).

The semiconductor dies used in the semiconductor packages according topreferred embodiments of the invention include vertical powertransistors. Vertical power transistors include VDMOS transistors. AVDMOS transistor is a MOSFET that has two or more semiconductor regionsformed by diffusion. It has a source region, a drain region, and a gate.The device is vertical in that the source region and the drain regionare at opposite surfaces of the semiconductor die. The gate may be atrenched gate structure or a planar gate structure, and is formed at thesame surface as the source region. Trenched gate structures arepreferred, since trenched gate structures are narrower and occupy lessspace than planar gate structures. During operation, the current flowfrom the source region to the drain region in a VDMOS device issubstantially perpendicular to the die surfaces. An example of asemiconductor die 800 comprising a vertical MOSFET with a trenched gateis shown in FIG. 21. Other devices that may be present in asemiconductor die may include diodes, BJT (bipolar junction transistors)and other types of electrical devices.

Referring again to FIG. 3, part of the leadframe 214 may be etched toallow the molding material 13 to lock to the leadframe. As shown in FIG.3, the gate lead structure 11 has a gate pad 31 and a partially etchedregion 31(a) for locking. The source lead structure 214(a) has anexposed source pad 14 with an exposed source pad surface 14(a). Thesource pad surface 14(a) is also defined by a partially etched region 34for mold locking. The source pad surface 14(a) may be part of aprotruding region that protrudes from the other portions of the sourcepad 14.

As shown in FIG. 4, the drain clip 15 may also be partially etched, andmay have a partially etched region 311 to allow the molding material 13to lock to the drain clip 15. The drain pad surface 15(a) may be part ofa protruding region that protrudes from the other portion of the sourcepad.

Any suitable etching process may be used to etch the leadframe and/orthe clip 15, and etching may occur to any suitable depth. Suitableetching processes may include wet or dry etching processes. In someembodiments, the leadframe may be etched about one half way through thethickness of the leadframe. The etched leadframe maybe characterized asbeing half-etched under such circumstances.

FIG. 5 shows a top perspective view of the semiconductor die package 10with a portion of the molding material 13 being removed. As shown, themolding material 13 may cover ledges forming the partially etchedregions 31(a), 34 of the leadframe 214, without covering the source padsurface 14(a). The top exterior surface of the molding material 13 maybe substantially coplanar with the source pad surface 14(a). As shown inFIG. 1, the molding material 13 may cover the top surface 31(b) of thegate pad 31. The top surface 31(b) of the gate pad 31 may be exposed,however, in other embodiments of the invention.

FIG. 6 shows a bottom perspective view of the semiconductor die packagewith a portion of the molding material 13 being removed. FIG. 6 moreclearly shows the partially etched region 311 of the clip 15. Themolding material 13 may cover the surfaces of the partially etchedregion 311, but does not cover the drain surface 15(a). The drainsurface 15(a) can be substantially coplanar with the bottom exteriorsurface of the molding material 13. As shown, the clip 15 may also havelateral grooves 127 improve the locking of the molding material 13 tothe clip 15.

FIG. 7 is a cross-sectional view of the semiconductor die package. FIG.7 more clearly shows solder bumps 76 coupling a first surface 32(a) ofthe semiconductor die 32 to the source pad 14. Solder paste 99 maycontact the solder bumps 76 and the source pad 14. The semiconductor die32 may also comprise a second surface 32(b) that is coupled to the drainclip 15. Solder can also be used to couple a second surface 15(b) of thedrain clip 15 to the second surface 32(b) of the semiconductor die 32.The molding material 13 does not cover the top first surface 14(a) ofthe source pad 14 and the bottom surface of the clip 15, and furtherfills in the partially etched region 311 to allow the molding material13 to lock to the drain clip 15. As shown in FIG. 7, the bottom surface15(a) of the clip 15 is also substantially coplanar with the bottomsurface of the molding material 13. In this example, source leads 12extend from one side of the semiconductor die package, while the drainclip 15 extends from the opposite side of the semiconductor die package.

The solder bumps 76 and the solder paste 99 may have different meltingtemperatures in some embodiments of the invention, and any suitablesolder material may be used including Pb based solder and lead freesolder materials. Other types of conductive adhesives such as conductiveepoxies may also be used to electrical and mechanically couple parts inthe package 10 together.

FIG. 8 shows a front cross-sectional view of the semiconductor diepackage 10 in FIG. 7. FIG. 8 additionally shows a partially etchedregion 34 of the source pad 14, and the molding material 13 filling inthe partially etched region 34 to provide for molding locking.

FIG. 9 shows an exploded view of the previously described leadframe 214,molding material 13, semiconductor die 32, and the clip 15.

FIG. 10 shows a top view of the semiconductor die package 10.

A method for forming the above described semiconductor die package cannow be described. In one embodiment, the method may comprise obtaining asemiconductor die comprising an input at a first top semiconductor diesurface and an output at a second bottom semiconductor die surface, andattaching a leadframe having a first leadframe surface and a secondleadframe surface opposite the first leadframe surface to thesemiconductor die. The second leadframe surface is coupled to the firsttop semiconductor die surface. A clip having a first clip surface and asecond clip surface is attached to the semiconductor die before or afterthe semiconductor die is attached to the second leadframe surface. Inany event, the second clip surface is coupled to the second bottomsemiconductor die surface, and a molding material is molded around atleast a portion of the leadframe, the clip, and the semiconductor die,wherein after molding, the first leadframe surface and the first clipsurface are exposed by the molding material, and wherein the firstleadframe surface, the first clip surface, and the exterior moldingmaterial surfaces of the molding material form exterior surfaces of thesemiconductor die package.

A leadframe can be obtained from any suitable precursor structure, whichmay be formed by any suitable process including stamping, etching, orany suitable combination of such processes. FIG. 11 shows a topperspective view of a leadframe precursor structure 111 according to anembodiment of the invention. It includes a lifted anvil 113 at a firstend of the leadframe precursor structure 111 attached to a frame 112.The frame 112 may define a frame window 1111 for molding. The uppersurface of the anvil 113 may lie in a different plane and may be downsetwith respect to the upper surface of the frame 112. A horizontal slot1112 is parallel to the orientation of the anvil 113 and two verticallocator slots 1113 on opposite ends of the horizontal slot 1112. Thevertical slots 1113 will be used for thermal drain clip hookpositioning.

The leadframe precursor structure 1111 also includes a source leadstructure including a source pad 14 and integral source leads 12, and agate lead structure including a gate pad 31 and an integral gate lead11, attached to the frame 112 via tie bars 118 at a second end oppositethe first end. As in prior FIGS., partially etched regions 34 and 31(a)are shown in the source pad 14 and the gate pad 31, respectively.

FIG. 12 shows a perspective view of the drain clip 15. It includes adrain clip surface 15(a), and slotted regions 127 for mold locking, aswell as a relief slot 126 for cutting in a singulation process. It alsoincludes a thermal clip locator hook 125 extending from a thermal clippad 124. The drain clip 15 can be formed by any suitable processincluding etching and stamping.

FIG. 13 shows the leadframe precursor structure 111 in FIG. 11, flippedover. FIG. 13 shows a support area 1216 for the clip 15 on the anvil113. Solder paste 1215 is on the support area 1216. Solder paste 99 isalso deposited on the internal surfaces of the gate pad and the sourcepad. A flat frame surface 1213 is also present in the leadframeprecursor structure 111.

FIG. 14 shows a perspective bottom view of an assembled frame with anattached thermal drain clip. FIG. 15 shows a top perspective view of theassembled frame with an attached drain clip. FIG. 15 also shows athermal die attach clip pad 159. FIG. 18 shows a cross-sectional view ofthe assembly shown in FIGS. 16-17. FIG. 18 additionally shows aconductive adhesive (e.g., solder) 186 coupling the die 32 to the drainclip 15, and a setting point 1710 between the clip 15 and the anvil 113.

As shown in FIG. 14, the clip 15 can be placed on the source and gatepads so that the hook 125 fits into the horizontal slot 1112. Oppositeedges defining the vertical slots 1113 restrict the lateral movement ofthe hook 125, thereby stabilizing the lateral and vertical positioningof the clip 15, relative to the source and gate pads 14, 31 (See FIG.15). As shown in prior Figures, a semiconductor die 32 is sandwichedbetween the source and gate pads 14, 31, and the drain clip 15. Thesemiconductor die 32 may have been bumped with solder using conventionalsolder deposition processes.

As shown in FIGS. 16 and 17, after attaching a semiconductor die 32 tothe precursor 111 and the clip 15, a molding material 113 can be formedso that it covers at least a portion of the semiconductor die 32, theframe 214 in the precursor 111, and the clip 15. As shown in FIG. 16,the top surfaces of the source pad 14, gate lead 11, and source leads12, are exposed by the molding material 13, and may be substantiallycoplanar with the top exterior surface of the molding material 13. Asshown in FIG. 17, the bottom surface of the drain clip 15 issubstantially coplanar with the bottom surface of the molding material13. The molding material 13 lies within a frame window 179 formed by theleadframe precursor 111.

Molding may occur using any suitable molding tool or molding process. Inan exemplary embodiment, the molding tool may have two molding dies,where surfaces of the molding dies contact surfaces of the leadframe andthe clip so that they are not covered with molding material during themolding process. Any suitable molding temperatures and pressures may beused in embodiments of the invention.

After molding, referring to FIGS. 16-17, the leads 11, 12 as well as theportion of clip 15 with the slot 124 may be cut with a saw or the like.The leads 11, 12, may then be bent (if they are not already bent) toform the semiconductor die package.

Although one semiconductor die package is shown, the semiconductor diepackage may be formed in an array.

FIGS. 19( a)-19(b) show top plan views of assemblies like those shown inFIGS. 16-18, which two different die sizes. FIG. 19( a) shows a die sizeof 2.66 mm×3.66 mm. FIG. 19( b) shows a die size of 4 mm×4 mm.Accordingly, as shown in FIGS. 19( a)-19(b), embodiments of theinvention may incorporate any suitable die size, or type of die.

FIGS. 20( a)-20(k) show portions of a semiconductor die package as it isbeing formed. Many of the steps in FIGS. 20( a)-20(k) have beendescribed above, and the descriptions are applicable here.

FIGS. 20( a)-20(k) show the following: FIG. 20( a) shows a thermal drainclip 15; FIG. 20( b) shows a die 32 being attached to the thermal drainclip 15 using a soft solder and die attach process (using reflow); FIGS.20( c)-20(d) show a structure formed after singulation and subsequentplacement (by flipping) of the clip 15 and die 32 combination onto aleadframe precursor 111; FIG. 20( e) shows a structure formed after areflow process is performed, wherein the die 32, the clip 15, and theprecursor 111 are joined together; FIG. 20(f) shows a structure formedafter a film assisted molding process is performed, whereby a moldingmaterial 13 is formed around selected parts of the package; FIG. 20( g)shows a structure formed after a water jet deflash process is performed;FIG. 20( h) shows a structure formed after a laser marking process isperformed, whereby the die package can be laser marked foridentification purposes; FIG. 20( i) shows a structure formed after asingulation process is performed, whereby the package can be separatedfrom other packages in an array; FIG. 20( j) shows a structure formedafter a unit test step is performed; and FIG. 20( k) shows a structureformed just prior to a pack and ship step.

Embodiments of the invention have a number of advantages. Embodiments ofthe invention may have some, none or all of the following advantages.First, by exposing portions of the leadframe and clip through themolding material, the packages are quite thin and can be used in thindevices such as wireless phones, PDAs, etc. Second, since largersurfaces of the clip and the leadframe are exposed, heat can easilydissipate from a semiconductor die within a semiconductor die packageaccording to an embodiment of the invention. Third, bigger die sizes canbe mounted using the same standard footprint. Fourth, as noted above, aclip can be properly aligned with a die and a leadframe using a hook,thereby reducing potential alignment errors during manufacturing. Fifth,no deflash process and plating processes are needed if a pre-platedframe is used. Sixth, embodiments of the invention are flexible and canuse both copper stud bumping and electroless NiAu bumps as well. Suchbumps may be present on the previously described dies. Seventh,embodiments of the invention are robust and can be used in applicationssuch as automotive applications. Eighth, there is no need to use a filmassisted mold process since both sides of the package can be inmetal-to-metal contact with the surfaces of a mold cavity.

As used herein “top” and “bottom” surfaces are used in the context ofrelativity with respect to a circuit board upon which the semiconductordie packages according to embodiments of the invention are mounted. Suchpositional terms may or may not refer to absolute positions of suchpackages.

The semiconductor die packages described above can be used in electricalassemblies including circuit boards with the packages mounted thereon.They may also be used in systems such as phones, computers, etc.

Any recitation of “a”, “an”, and “the” is intended to mean one or moreunless specifically indicated to the contrary.

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention inthe use of such terms and expressions of excluding equivalents of thefeatures shown and described, it being recognized that variousmodifications are possible within the scope of the invention claimed.

Moreover, one or more features of one or more embodiments of theinvention may be combined with one or more features of other embodimentsof the invention without departing from the scope of the invention.

All patents, patent applications, publications, and descriptionsmentioned above are herein incorporated by reference in their entiretyfor all purposes. None is admitted to be prior art.

1. A semiconductor die package comprising: a semiconductor diecomprising an input at a first top semiconductor die surface and anoutput at a second bottom semiconductor die surface; a leadframe havinga first leadframe surface and a second leadframe surface opposite thefirst leadframe surface, wherein the second leadframe surface is coupledto the first top semiconductor die surface; a clip having a first clipsurface and a second clip surface, wherein the second clip surface iscoupled to the second bottom semiconductor die surface; and a moldingmaterial having exterior molding material surfaces and covering at leasta portion of the leadframe, the clip, and the semiconductor die, whereinthe first leadframe surface and the first clip surface are exposed bythe molding material, and wherein the first leadframe surface, the firstclip surface, and the exterior molding material surfaces of the moldingmaterial form exterior surfaces of the semiconductor die package.
 2. Thesemiconductor die package of claim 1 wherein the semiconductor diecomprises a vertical device.
 3. The semiconductor die package of claim 1wherein the first leadframe surface defines a protruding leadframeportion of the leadframe.
 4. The semiconductor die package of claim 3wherein the first clip surface defines a protruding clip portion of theclip.
 5. The semiconductor die package of claim 3 wherein exteriorsurfaces of the molding material are substantially coplanar with thefirst clip surface and the first leadframe surface, and wherein themolding material covers edges of the protruding leadframe portion andthe protruding clip portion.
 6. The semiconductor die package of claim 1wherein the semiconductor die is coupled to the leadframe using solder.7. The semiconductor die package of claim 1 wherein the solder comprisesa high temperature solder material and a low temperature soldermaterial.
 8. The semiconductor die package of claim 1 wherein thesemiconductor die comprises a trenched gate.
 9. The semiconductor diepackage of claim 1 wherein the leadframe comprises copper or a copperalloy.
 10. A system comprising the semiconductor die package of claim 1.11. A method for forming a semiconductor die package, the methodcomprising: obtaining a semiconductor die comprising an input at a firsttop semiconductor die surface and an output at a second bottomsemiconductor die surface; attaching a leadframe having a firstleadframe surface and a second leadframe surface opposite the firstleadframe surface to the semiconductor die, wherein the second leadframesurface is coupled to the first top semiconductor die surface; attachinga clip having a first clip surface and a second clip surface, whereinthe second clip surface is coupled to the second bottom semiconductordie surface; and molding a molding material around at least a portion ofthe leadframe, the clip, and the semiconductor die, wherein aftermolding, the first leadframe surface and the first clip surface areexposed by the molding material, and wherein the first leadframesurface, the first clip surface, and the exterior molding materialsurfaces of the molding material form exterior surfaces of thesemiconductor die package.
 12. The method of claim 11 wherein attachingthe leadframe to the semiconductor die comprises using solder to attachthe leadframe to the semiconductor die.
 13. The method of claim 11wherein attaching the clip to the semiconductor die comprises usingsolder to attach the clip to the semiconductor die.
 14. The method ofclaim 11 further comprising, prior to attaching the leadframe to thesemiconductor die, partially etching the leadframe to form a protrudingportion comprising the first leadframe surface.
 15. The method of claim14 further comprising, prior to attaching the clip to the semiconductordie, partially etching the clip to form a protruding portion comprisingthe first clip surface.
 16. The method of claim 14 wherein moldingcomprises using a molding tool with molding dies that contact surfacesof the clip and the leadframe.
 17. The method of claim 14 wherein thesemiconductor die comprises a vertical MOSFET.
 18. The method of claim14 wherein the leadframe comprises copper.
 19. The method of claim 14wherein attaching the leadframe to the semiconductor die occurs afterattaching the clip to the semiconductor die.
 20. The method of claim 14wherein the semiconductor die package is in an array of semiconductordie packages when the semiconductor die package is formed.